1. Field of the Invention
The present invention relates to a method and apparatus that facilitates delay tuning of integrated circuits and, in particular, to a method and apparatus for providing a software implementation of delay tuning in integrated circuits.
2. Description of the Prior Art
Timing analysis is a critical element of the design of an integrated circuit. Vendors of integrated circuits often standardize the performance of their circuits to ensure that they meet a standardized timing scheme. The scheme may be the subject of a market-wide standard or may be established by the vendor itself. Often, the vendors distribute timing diagrams with their products to permit purchasers to integrate the products into larger designs. Thus, uniform, consistent timing performance is critical to market success of integrated circuits.
Consider the circuit of FIG. 1, for example. There, a microprocessor (xcexcP) generates an address signal on, for example, sixteen (16) parallel address lines, labeled A0-A15. Due to characteristics of the circuitry that generates the address signals, the signals may be skewed: They may not be established in unison. Certain lines may become active before certain others. This performance may cause the microprocessor to deviate from the requirements of an established timing protocol.
Each address signal A0-A15 may be generated by the circuit of FIG. 2. There, a master slave flip flop 210 receives a data signal (the address data) generated from within the microprocessor. The flip flop 210 captures the data signal when triggered by a clock signal 220 and outputs the data signal thereafter. Typical trigger signals are the rising edge or the falling edge of the clock. Because the data signal may not be established at the flip flop input when the triggering signal is received from the clock, a delay circuit 240 may be added to delay propagation of the clock to the flip flop.
Excessive delays contribute to loss of data. New data may overcome old data before the old data is clocked into the flip flop 210. Accordingly, a latch 200 is provided between the source of the data signal and the flip flop. The latch 200 itself is clocked by a non-delayed clock signal 200. Under this scheme, old data may be clocked into the flip flop 210 before new data is input to the latch 200.
During circuit design, an amount of desired delay is unknown. Therefore, delay circuits are tuned. FIG. 3 illustrates the configuration of a known delay circuit 240 for a single data line. There, the circuit provides a plurality of alternate paths 242-246 for a data signal. Each path provides a different number of delay buffers in the path. Each delay buffer imposes an incremental amount of delay upon the signal. Thus, the selection of a path determines how much delay is imposed on the signal.
Through trial and error, technicians alternately direct the signal through each of the delay paths 242-246 to determine how much delay is necessary to meet desired timing requirements. The trial and error procedure is implemented in a physical prototype of the integrated circuit. To direct the signal through a particular delay path, a technician must establish a physical electrical connection to test a first path, test it, then destroy the connection and establish a second connection to test a second path. Once a preferred delay path is identified for the particular signal, the selected delay path becomes part of the design of the integrated circuit.
A single integrated circuit may have several hundred delay circuits. Every delay circuit within the integrated circuit must be xe2x80x9ctunedxe2x80x9d through the trial and error process described above. Delay tuning, therefore, materially increases the time and expense of integrated circuit manufacture.
Accordingly, there is a need in the art for a delay tuning process that reduces time and expense associated with delay tuning. Further, there is a need for such a process that eliminates the need for providing physical interconnections between a signal and the alternate delay paths that the signal must traverse for testing.
An embodiment of the present invention provides a delay element that receives an input signal and imposes a variable delay upon the signal. The delay element includes a plurality of delay stages interconnected in a cascaded relationship. Each stage imposes an incremental delay upon the input signal when enabled. The delay element receives a selection signal that determines how many of the delay stages are enabled.